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[VHDL-FPGA-Veriloggeneric_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilogminiuart.tar

Description: Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.
Platform: | Size: 6144 | Author: eldis | Hits:

[Internet-NetworkBT_SDK_3.1

Description: 点量BT 3.1版本: 1、修改为Unicode的参数方式,以方便的支持日韩等文件名 2、开放多个原来商业版的接口到免费演示版,使免费演示版功能更为丰富。 3、修正Delphi下调用接口名字有时候会变化的问题 4、修正一些bug 5、优化内核对非UTF-8种子的处理,兼容性更好 6、全面优化内部处理,更好的兼容Bitcomet等BT软件,实现更快的下载速度;目前,点量BT内核是速度最快的商业性DLL内核。 7、优化内存结构,减少1/3左右的内存占用。 8、修改为静态链接,去掉发布时需要附带Msvc71r.dll等文件的问题 点量BT 3.0.0.1版本:更新libeay32.dll文件,避免文件依赖MSVCR90.dll 点量BT 3.0版本: 1、引入代理设置。 2、加入加密协议和加密数据功能,进一步突破运营商的封锁和限制。 3、制作种子加入进度显示 4、修正一些Bug-BT 3.1-point version: 1, modify the parameters for Unicode means to facilitate the support of Japan and South Korea, such as file name 2, open more than the original commercial version of the interface to the free demo version, so that a free demo version features even richer. 3, as amended, under Delphi Call Interface names sometimes change problem 4, amended a number of bug 5, and optimize the kernel for non-UTF-8 seed treatment, better compatibility 6, fully optimize the internal processing, better BT software compatible with BitComet, etc., achieve faster download speed At present, the BT-point cores are the fastest growing commercial core DLL. 7, Optimize the memory structure, a decrease of 1/3 of the memory footprint. 8, modified as a static link, removed when it is published and other required documents attached Msvc71r.dll questions BT 3.0.0.1-point version: update the libeay32.dll file, to avoid dependence on MSVCR90.dll file BT 3.0-point version:
Platform: | Size: 2514944 | Author: 小主 | Hits:

[OtherMpi-Omp_MatInf_blkstp

Description: This a mutlicore and cluster(of single-core,multi-core systems) matrix inversion code. Which uses the MPI(Message Passing Interface) for communication across the compute nodes of cluster and using thread-API based OpenMP(Open Multi Processing) between cores of intra-compute or head node.-This is a mutlicore and cluster(of single-core,multi-core systems) matrix inversion code. Which uses the MPI(Message Passing Interface) for communication across the compute nodes of cluster and using thread-API based OpenMP(Open Multi Processing) between cores of intra-compute or head node.
Platform: | Size: 2048 | Author: shraddha | Hits:

[VHDL-FPGA-Verilog10GOpenCore

Description: 10G Open Cores MAC which is implemented using vhdl langauge
Platform: | Size: 67584 | Author: ahmed | Hits:

[MPIpp-1.5.7RC

Description: Parallel Python (PP) PP is a python module which provides mechanism for parallel execution of python code on SMP (systems with multiple processors or cores) and clusters (computers connected via network). It is light, easy to install and integrate with other python software. PP is an open source and cross-platform module written in pure python-Parallel Python (PP) PP is a python module which provides mechanism for parallel execution of python code on SMP (systems with multiple processors or cores) and clusters (computers connected via network). It is light, easy to install and integrate with other python software. PP is an open source and cross-platform module written in pure python
Platform: | Size: 35840 | Author: gaolu | Hits:

[VHDL-FPGA-Verilogopencore_crt

Description: 可以在Altera QuartusII下编译的Open Cores PCI桥源代码,是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
Platform: | Size: 683008 | Author: Joe | Hits:

[matlabSVDSTest

Description: SDVS(a,k) test for matlabpool open local 8 Run in Xeon 8 cores
Platform: | Size: 313344 | Author: taltek | Hits:

[VHDL-FPGA-Verilogrsa_512_latest.tar

Description: 512位RSA VHDL 算法,使用了蒙哥马利模乘算法,该程序写的有些麻烦,但是对于初学者学习是够了。-512 bit RSA VHDL algorithm,it is open cores.it is very good for beginers to study.
Platform: | Size: 239616 | Author: 呼延郎 | Hits:

[VHDL-FPGA-Verilog512_RSA

Description: 512位RSA VHDL 算法,使用了蒙哥马利模乘算法,该程序写的有些麻烦,但是对于初学者学习是够了。-512 bit RSA VHDL algorithm,it is open cores.it is very good for beginers to study.
Platform: | Size: 13312 | Author: 呼延郎 | Hits:

[VHDL-FPGA-Verilogoc_i2c_master

Description: open cores 提供的i2c控制IP核 可直接在FPGA上使用。并带有相关的测试程序-endorsed by the i2c controller IP provided by the open cores on the FPGA. With the relevant test procedures
Platform: | Size: 273408 | Author: jine | Hits:

[mpeg mp3sgmedia

Description: 这是原来的“宋哥口袋播放器”改造完成,播放功能已经全面完成,有四个内核。不过我在设置窗口里屏蔽了后两个内核,因为不太稳定。还有一些功能未完成,完成后会发上来的。 打开源码前请将目录中vp.fne支持库拷到易语言lib目录下安装。 另:附赠“宋哥口袋播放器”源码。两个播放器使用相同的赤霄内存皮肤模块。 声明:四个内核只是借用别人或系统的,要研究解码器调用的勿进,否则只能白白扣点!-This is the original "Song Columbia pocket player" transformation was complete, the playback function has been fully completed, with four cores. But I am shielded in the settings window after the two cores, because of the less stable. Some features are not complete, finished hair up.Set directory vp.fne support the open source library copying the lib directory of easy language to install.Other: comes with "Song Columbia pocket player" source. The two players use the same skin of red Xiao memory module.Disclaimer: four cores just borrow other people or systems, the decoder call is strictly forbidden, or only a vain point deduction!
Platform: | Size: 5685248 | Author: 宋梓睿 | Hits:

[WEB Codexuyuan

Description: 此版本的许愿墙内核来自互联网一款老的源码,经过稍微修饰同样的分享出来提供大家在即将到来的2013年元旦节使用。我们可以给自己的网站提高人气互动,或者可以用来在QQ群之间的传播。 使用方法: 直接把文件丢进二级或者根目录均可,空间必须为ASP空间,直接打开网址就可以使用。-This version of Wishing Wall cores from the Internet an old source code, after slightly modified the same share with everybody in the coming New Year s Day 2013 use. We can give our own website improve popularity interaction, or can be used in the communication between the QQ group. Method of use: Directly to the file to drop into the two level or the root directory can be, space must be ASP space, directly open the URL you can use.
Platform: | Size: 173056 | Author: dfgsfwaoi | Hits:

[VHDL-FPGA-Verilogor1200_ep3c16_board

Description: OpenRisc是OpenCores组织提供的基于GPL协议的开放源代码的RISC(精简指令集计算机)处理器。有人认为其性能介于ARM7和ARM9之间,适合一般的嵌入式系统使用。最重要的一点是OpenCores组织提供了大量的开放源代码IP核供研究人员使用,因此对于一般的开发单位具有很大的吸引力。-OpenRisc is based organizations OpenCores the GPL open source RISC (Reduced Instruction Set Computer) processor. Some people think that the performance between the ARM7 and ARM9, an embedded system for general use. The most important point is OpenCores organization provides a number of open-source IP cores for researchers to use, so for the average developer is very attractive.
Platform: | Size: 260096 | Author: 程浩武 | Hits:

[VHDL-FPGA-Veriloguart_latest.tar

Description: 串行UART开源的核心。该设计是专为使用作为一个独立的芯片或用于与其他我们芯的使用。其原因显影串行UART核的事实,即异步串行通信是很常见的,几乎每一个机器理解it.Also,为OCRP-1,我们需要的通信的方式与主计算机,以使它可通过网。-serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.
Platform: | Size: 9216 | Author: | Hits:

[Documentsdma_axi (1)

Description: THIS IS DMA OPEN CORES THAT IS AVAILABLE OVER INTERNET
Platform: | Size: 2225152 | Author: bhavubhavanii | Hits:

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